Generally, the speed at which an integrated circuit operates is influenced by the distance between the farthest separated components that communicate with each other on the chip. Laying out circuits as three-dimensional structures has been shown to significantly reduce the communication path length between on-chip components, provided the vertical distances between the layers are much smaller than the chip width of the individual layers. Thus, by bonding and stacking circuit layers vertically, the overall chip speed is typically increased.
Wafer bonding is the joining of two or more semiconductor wafers on which integrated circuitry has been formed. Wafers may be joined by direct bonding of external oxide layers or by adding adhesives to inter-metal dielectric (IMD) layers. The bonded result produces a three-dimensional wafer stack, which may subsequently be diced into separate “stacked die,” with each individual stacked die having multiple layers of integrated circuitry. In addition to the increased speed that the three-dimensional circuitry typically experiences, wafer stacking offers other potential benefits, including improved form factors, lower costs, and greater integration through system-on-chip (SoC) solutions. In order to enable the various components integrated within each stacked die, electrical connections are provided that form conductors between vertical layers. Through silicon vias (TSVs) are typically fabricated to provide vias filled with a conducting material that pass completely through the substrate to contact and connect with the other TSVs and conductors of the bonded layers.
In various methods, TSVs are formed after the contact process, inter-level dielectrics (ILDs), or after the top metallization process, for example. The substrate may then be inverted and be ground down in a back-grind process to expose the TSVs. This method of exposing the TSVs may damage the structures, which may both lower yield and reduce product reliability. Further, TSVs may not be of uniform thickness. If the backside process does not compensate for non-uniformity, a percentage of TSVs may not be conducting in the substrate stack, causing failure of the device.